A modern DRAM memory cell consists of one MOS access transistor and one storage capacitor referred to as a one-transistor one-capacitor (1T1C) cell. The memory cell access transistor operates as a switch, interposed between the memory cell capacitor and a digitline. The memory cell is capable of holding a single piece of binary information, as stored electric charge in the cell capacitor. Given a bias voltage of Vcc/2 on the capacitor's common node, a logic one level is represented by +Vcc/2 volts across the capacitor and a logic zero is represented by -Vcc/2 volts across the capacitor.
The digitline consists of a conductive line connected to a multitude of memory cell transistors. Generally, either metal or polysilicon forms the conductive line. Due to the large quantity of attached memory cells, its physical length, and proximity to other features, the digitline is very capacitive.
The memory cell transistor's gate terminal connects to a wordline. The wordline, which connects to a multitude of memory cells, consists of an extended segment of the same polysilicon used to form the transistor's gate. The wordline is physically orthogonal to the digitline.
A pair of digitlines are typically fabricated as two adjacent digitlines. The digitlines are initially equilibrated at Vcc/2 volts, and all wordlines are initially at zero volts, which turns off the memory cell access transistors. To read a memory cell, its wordline transitions to a voltage that is at least one transistor V.sub.th above Vcc. This elevated wordline voltage level is referred to as Vccp or Vpp. When the wordline voltage exceeds one V.sub.th above the digitline equilibrate voltage (Vcc/2) and the memory cell access transistor turns on, the memory cell capacitor begins to discharge onto a digitline. Essentially, reading or accessing a memory cell results in charge sharing between the memory cell capacitor and the digitline capacitance. This sharing of charge causes the digitline voltage to either increase for a stored logic one or decrease for a stored logic zero. Ideally, the access will only modify the active digitline, leaving its complement digitline unaltered. Thus, a differential voltage develops between the two digitlines.
After the cell access is complete, a sensing operation is performed. The reason for forming a digitline pair is to allow for the use of a differential sense amplifier circuit. The sense amplifier typically consists of a cross-coupled PMOS transistor pair and a cross-coupled NMOS transistor pair. As discussed in the preceding paragraph, a signal voltage develops between the digitline pair when the memory cell access occurs. While one digitline contains charge from the cell access, the other digitline serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp fires first and the P-sense-amp second.
In another memory architecture, a common plate of the array of memory cell capacitors is used as a reference for the sense amplifier circuitry. This scheme, therefore, changes the traditional differential digitline sensing and equilibration operations. Using a common plate for the entire memory array creates a large capacitive reference which remains stable during memory accesses. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a new method of dynamic digitline sensing and equilibration where low voltage memories can experience larger differential voltages during memory read operations.